玛雅吧

0.18μm/0.16μm/0.153μm 1.8V/3.3V G
0.18μm/0.16μm/0.153μm 1.8V/5V G

 

 Overview

CSMC 0.18 micron process is process-matched to other foundry. CSMC logic process include Generic(G) and Low Power(LP). Each 0.18 micron process provide 1.8V operation voltage core device, 3.3V or 5V operation voltage IO device. 0.18 process option include native VT device, medium low VT device, isolation NMOS, MIM capacitor, high precision poly resistor, varactor and inductor.

Shrunk process is effective cost-down for customer and shrunk process provide device is very similar to non-shrunk process. 0.162 micron process is 90% shrunk of 0.18 micron process and 0.153 micron process is 85% shrunk of 0.18 micron process.

CSMC 0.18 micron process provide OTP/MTP process, OTP/MTP process no need extra mask layer.

 Key Features

		0.18G
Core Voltage	Typical	1.8V
Core Device	Typical VT	√
	Low VT	√
IO Device	3.3V	√
	5V	√
SRAM BItcell(um2)		4.65

 0.18um Process Family

		0.18G
Special Process	Mix	√
	RF	√
	OTP/MTP	√
Design	Technical File	√
	PDK	√
	IP/Library	√

 

 

 0.18μm CMOS EN (3.3V or 5V) 

 

 Overview  
        公司提供的0.18μm CMOS EN (3.3V or 5V)工艺占有极具竞争力的光刻次数和紧凑的设计规定
，为DC-DC、LED屏驱动、音频功放、MCU蹬爪用提供了很好的解决规划。

 

 Key Features 
- Single poly, rich metal (Aluminum) options (support 2~6, thin/thick top metal options)
- Hi-Rsh poly resistor, MIM/MOS capacitor, OTP/FT E–fuse and other rich device options
- Full Design Kit support with PDK\CMD\library

 

 Application 
- DC-DC
- LED display
- Audio amplifier
- MCU

 

 0.18μm e-Flash

 

 Overview  
        公司提供的0.18μm e-Flash工艺兼容0.18um logic工艺
，提供业界拥有竞争力的闪存IP
，高靠得住性
，低功耗和低成本
，为智能卡、各类屏接触节造、MCU蹬爪用提供了很好的解决规划。

 

 Key Features 
- Double polys, support 4~6 top metal options
- Industrial competitive flash macro cell size, low voltage, low power operation
- Full Design Kit support with PDK\ std cell\IO Library

 

 Application 
- Smart card
- Touch-screen controller
- MCU